With the emergence of 3D packaging technology, the term "more than Moore" has emerged to reflect that the growth rate of area circuit density exceeds the traditional IC scaling speed related to Moore's Law. At the design automation conference held in Las Vegas this year, numerous exhibits from suppliers showcased unique packaging technologies. However, advanced packaging technology also requires corresponding methodological processes, including all aspects of design, implementation, and (electrical heating) analysis. I had the opportunity to discuss with John Park, Director of Integrated Circuit Packaging and Cross Platform Solutions Product Management at Cadence, the process requirements for these packaging solutions.
Classification: SoC, SiP, and Chiplet
Multi Chip Module (MCM) technology has existed for decades and has been applied in very specific high-performance computing, communication, and aerospace applications. The engineering resources for developing physical implementations are considerable, and the investment in electrical analysis of chip packaging systems is also considerable
He also said, "There were two trends that followed. The expanding Moore's Law silicon technology introduced System on Chip (SoC) architecture, integrating IPs from multiple sources. At the same time, the signal and power I/O counts of these modules also increased. The introduction of 2.5D packaging technology, using interconnects on interpolators (or substrates), allowed these high pin counting modules to be integrated into a complete System Level Package (SiP), increasing the opportunities for SiP.". The 3D packaging technology using vertically stacked molds has only recently been launched, which puts special requirements on the EDA process, from limited test pin access to different thermal modeling requirements